One type of prior art flash Erasable and electrically Programmable Read-Only Memory ("flash EPROM")is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. The flash EPROM can have a blocked architecture by grouping a number of columns into one block. The flash EPROM can be programmed by a user. Once programmed, the flash EPROM retains its data until erased by electrical erasure. A high erasing voltage is made available to the sources of all the cells in a memory block simultaneously. This results in a block erasure. The flash EPROM can also have a full array erasure by applying the erasing voltage to the sources of all memory cells of the flash EPROM simultaneously. The erased block or array of the flash EPROM can then be reprogrammed with new data.
One type of prior art flash EPROM typically includes redundant memory cells. The redundant memory cells are used to replace defective cells of the main memory array. FIG. 1 shows one prior art redundancy scheme for a flash EPROM.
As can be seen from FIG. 1, flash EPROM 10 includes a main memory 11 that is organized into a number of memory blocks BLOCK0 through BLOCKn. Each block includes word lines and bit lines. The bit lines of a block extend only within the block while the word lines are shared by all the blocks. The array configuration of each block of memory array 11 is shown in FIG. 2.
As shown in FIG. 2, a block 25 of memory array 11 includes bit lines 21a and 21b and word lines 22a and 22b. Block 25 represents the array configuration of each of blocks BLOCK0 through BLOCKn. Word lines 22a and 22b extend beyond block 25 and bit lines 21a and 21b only extend within block 25. Memory cells 25a and 25c have their control gates connected to word line 22a and memory cells 25b and 25d have their control gates connected to word line 22b. The drains of cells 25a and 25b are connected to bit line 21a and the drains of cells 25c and 25d are connected to bit line 21b. The sources of cells 25a-25d are all connected to a source line 23.
Referring back to FIG. 1, each block of memory array 11 also includes a number of redundant columns. For example, BLOCK0 has redundant columns 12 and BLOCKn has redundant columns 12n. Each of the redundant columns within a block can replace one defective column within that block.
Because the word lines of memory array 11 extend to all the blocks of array 11, a redundant row that extends to all the blocks of array 11 is needed to replace a defective row of memory array 11. As can be seen from FIG. 1, memory array 11 includes redundant rows 13A. When rows of memory array 11 are found defective, redundant rows 13A are used to replace the defective row.
Disadvantages are, however, associated with this prior art redundancy scheme. One disadvantage associated is that such redundant arrangement sometimes may not be able to replace a defect in the main memory array. For example, as can be seen from FIG. 2, when word line 22a is shorted to bit line 21b through a defect connection 27, the redundancy scheme as shown in FIG. 1 cannot replace the defective row. This is due to the fact that the redundant rows can only replace the defective rows in the main array when the defective rows are shorted together. If only one row of the main memory array is found defective, the defective row will affect the memory operations of the adjacent rows of the defective row.
Moreover, another disadvantage of the prior art redundancy scheme is that when a block has more defective columns than the number of redundant columns provided, that block simply cannot be repaired by the prior art redundancy scheme even though other blocks may have unused redundant columns. Typically in a flash EPROM, a block has a limited number of redundant columns. This is due to the fact that the more redundant rows and columns within a given flash EPROM, the larger that flash EPROM becomes.
When the defect or defects in the main memory array cannot be fixed by the prior art redundancy scheme, the flash EPROM has to be discarded. The number of the discarded flash EPROM chips typically affects the overall cost of fabricating the flash EPROM. When the number of the discarded flash EPROM chips per silicon wafer increases, the overall fabrication cost of the flash EPROM increases accordingly.